verification environment
英 [ˌvɛrɪfɪˈkeɪʃən ɪnˈvaɪrənmənt]
美 [ˌvɛrəfəˈkeɪʃən ɪnˈvaɪrənmənt]
网络 验证环境
双语例句
- These services come into play mainly when applications move from the development environment to the verification environment and finally to the production environment.
这些服务主要在应用程序从开发环境转移到验证环境并最终转移到生产环境时发挥作用。 - Overall the verification environment development time turned out to be far less time consuming and more predictable than OKI's previous approach.
结果证明，整体上该验证环境的开发耗时更短、且比OKI的前一种方法更具可预测性。 - Realizing Class-Based High Efficiency Simulation& Verification Environment with OVM
利用OVM实现基于Class的高效仿真验证环境 - Setup and Applications of the Co-Formal Verification Environment Co-Formal
协同形式验证环境Co-Formal的建立与应用 - Research on Developing Method of SoC Verification Environment
SoC验证环境搭建方法的研究 - Now the verification environment has been used in projects and research.
目前该验证系统已应用于工程实践和教学研究中。 - The co verification environment consists of an embedded software debugger and an embedded hardware simulator. It adopts instruction set architecture co simulation model.
该协同验证环境由嵌入式软件调试器和嵌入式硬件模拟器组成，其采用了指令集结构的协同模拟模型。 - ERES-ET is a computer design simulation and verification environment which was developed by Fudan university and East China Institute of Computer Technologies.
ERES-ET是复旦大学与华东计算技术研究所合作研制的计算机设计模拟验证环境。 - When we build the verification platform, we study the state-of-art commercial verification platform, raise the unified verification environment, and put it into practice.
在搭建验证系统时，仔细分析现有商业验证平台，结合它们的设计优点，我们提出了自己的统一验证环境的指导思想。 - Last, we construct an automatic verification environment based on the multiprocessor system in order to fully verify the Cache-coherent protocol.
构建了一个基于多处理器系统的自动验证环境，对所设计实现的Cache一致性协议的正确性予以了充分的测试验证。 - Reusing block level verification environment in top level is an efficient way to improve productivity. Synopsys? NTB can conveniently achieve this reuse.
模块级验证环境在顶层验证中的复用可以有效地提高生产率，利用Synopsys先进的NTB验证语言可以方便地实现验证环境复用。 - In order to complete the avionic system emulation/ verification/ experiment in laboratory, it is necessary to establish the avionic emulation/ verification environment.
为了完成飞机航空电子系统在地面的仿真/验证/试验，必须建立航空电子仿真/验证环境。 - The system includes the behavior level description of MPRS simulator, the programming environment and verification environment.
该系统不仅包括在系统行为层次上描述的MPRS模拟器，还包括编程环境和验证环境，为整个论文的工作提供了研究平台。 - This paper introduces verification of AMBA AHB-compatible interface logic of a CPU chip, including verification environment, mechanism for data generation and data checking.
本文介绍了一款CPU芯片的AMBAAHB接口逻辑的设计验证工作，包括整体的验证环境，数据产生机制，以及数据检查机制。 - The paper introduces classification and vector, especially describes functionality verification environment, then proposes a new envionment to improve the efficiency and correctness of verification vector.
简要介绍了测试分类及测试向量，重点描述功能验证环境的建立，并提出一种新的功能验证环境，用于提高测试向量产生的效率和准确率。 - Eres-et& a simulation and verification environment for computer design
ERES-ET计算机设计的模拟验证环境 - This paper brings forward a building scheme of atpg-based ASIC verification environment. It has integrated C, TCL and Verilog HDL languages to achieve good practicability and expansibility.
文章提出了一种基于自动测试向量生成（ATPG）的ASIC前端验证环境的构建方案，方案整合C，TCL和Ver鄄ilogHDL语言，有着良好的实用性和可扩展性。 - Modern SOC system will contain cores ( CPU or DSP). All the test cases based on this verification environment are executed through the soft SOC core of RTL.
现代SOC系统中都会包含核（CPU或者DSP），在基于本文所搭建的环境的测试用例中，所有测试用例都是通过SOCRTL中的软核来执行的。 - Through high level abstraction modeling method, we designed virtual SoC platform including systematic function models and peripheral device behavior models, providing one uniform verification environment for different IPs.
通过高层抽象建模方法，设计了包括系统级功能模型与外设行为模型在内的虚拟SoC平台，为不同IP提供统一的验证环境。 - High degree can be configured in the SoC chip verification process, different stages require different verification environment, and authentication, or authentication at the same stage of validation of different modules also need to change part of the verification environment.
第三.可配置程度高，在SoC芯片验证流程中，不同的阶段需要不同的验证环境和验证方式，或者在相同阶段验证对不同的模块进行验证也需要对改变验证环境的部分内容。 - System Verilog ( SV) is applied as the language of verification environment. And its advanced technologies are used to design verification environment and its components. 3.
采用systemverilog（SV）作为验证环境的设计语言，并利用此语言的各项高级验证技术进行验证环境的搭建和组件设计。 - Furthermore, we design an UML-based software testing and verification environment based on the researches of UML testing and verification, and implement the prototype.
此外，根据我们对UML测试和验证的研究成果，设计了一个基于UML的软件测试和验证环境的体系结构，并实现了原型系统。 - The platform united with system-level simulation platform comes to an integrated NoC Development verification environment with system analysis, functional simulation, hardware verification and performance evaluation functions. 7.
该平台和系统级仿真平台结合可以形成一个集片上网络系统分析、功能仿真、硬件验证和性能评估的完整的片上网络开发验证环境。 - It detailedly described the verification environment, through testing environment designed to meet the scheduled inspection requirements, the design has been applied to the product.
详细描述了验证环境，通过测试环境检验设计达到了预定要求，设计已应用于实际产品。 - The mechanism for scheduling and management of two kinds of software are built up, and the software is implanted into the verification environment. 4.
完成软件验证环境的搭建，建立两种软件的调度与管理机制，并将软件嵌入到验证环境。 - The speed of FPGA-based verification is faster compared to the first two. FPGA verification environment is very close to the real environment of the chip design. Firstly, the paper introduces the two main verification methods, formal verification and functional verification.
基于FPGA的验证速度虽然没有硬件验证快，但是明显快于前两者，而且FPGA的验证环境是非常接近芯片设计的真实环境的。论文首先介绍了两种主要的验证方法，形式验证和功能验证。 - The data and services collected by this platform provide experiment and verification environment for composition applied research.
该平台采集的数据及服务为组合Web服务的应用研究提供了实验和验证的环境。 - For the lack of observability and controlling, poor reusability of verification environment, not locating design faults immediately in the verification process, the traditional verification methods cannot meet the needs of Very Large Scale Integrated Circuit design nowadays.
传统的验证方法由于存在验证过程中的可观察性和可控制性不足，验证环境可重用性差，无法快速定位设计缺陷等缺点，已经无法满足现今超大规模集成电路设计的需要。 - Usually, Chip design and verification are carrying out in parallel: dividing the test points, setting up verification environment, selecting verification method and writing case for testing are required in the verification step.
通常对芯片的设计和验证工作同时进行：验证阶段需要分解测试点，搭建验证环境，选择验证方法，编写测试用例。